Not applicable.
As is known in the art, semiconductor integrated circuits or xe2x80x9cchipsxe2x80x9d are typically tested at three temperatures prior to shipment or inclusion in a larger device or module. While much of the testing is done at room temperature, since temperature can affect the performance of a semiconductor device, most chips are also tested at a cold temperature and a hot temperature.
To provide testing at multiple temperatures, a handling device that presents the chips to the tester often includes temperature conditioning chambers called soak chambers and de-soak chambers. In a soak chamber, the chips are heated or cooled to the desired test temperature. The chips are then moved to a test chamber where they are tested by placing and pressing them against electrical test contactors which are provided as part of the test chamber. The temperature of the test chamber is typically held at the desired test temperature. After testing the chips, the chips are moved to the de-soak chamber. The temperature of the de-soak chamber is selected to return the chips to room temperature.
A significant amount of time is required to heat or cool trays of chips to the required test temperature. The chambers must thus be large enough to hold several batches of chips so that there is always one batch at the required temperature. In addition, mechanical systems to move the chips between the various chambers are needed. A handling device having sufficient soak and de-soak chambers for testing at three temperatures would thus be relatively large and complex. Consequently, even though handlers can test a both hot and cold temperatures, many handlers are set up to test only at a hot or a cold temperature, but not both. Thus, there is delay in testing and moving the chips from one machine to another.
In one particular technique referred to as dynamic tri-temp, the chips are held against the electrical test contactors in a test chamber and the chips are rapidly heated or cooled to the required test temperature. Thus, testing at three temperatures is possible without moving the chips from the test chamber or off the electrical test contactors. This simplifies the testing process and, provided that the temperature of the chips can be changed quickly, can also speed up the testing process.
To ensure accurate results during testing, the temperature of the chip or device being tested must be controlled. It is, however, relatively difficult to control the temperature of the chips since due to advances on chip design and semiconductor manufacturing techniques the physical size and thermal mass of the chips has decreased while at the same time the amount of power dissipated by the chips has increased. As a result, chips now tend to heat rapidly during operation. If the test fixture in which the chips are tested does not have a thermal mass which is relatively low compared to the thermal mass of the chips being tested, it becomes difficult to rapidly switch the temperature of the device between a relatively high temperature and a relatively low temperature since it is necessary to also change the temperature of the test fixture.
It would, therefore, be desirable to provide a system for controlling the temperature of a device during dynamic tri-temp testing which has a relatively fast temperature response as well as good stability once a temperature set point is reached. It would also be desirable to provide a system which can be disposed in a relatively small test chamber. It would be further desirable to provide a system which allows good electrical contact to be made between a device under test and a tester. It would be still further desirable to provide a system in which many chips can be tested simultaneously.
One object of this invention is to provide a semiconductor structure for controlling the temperature of a device.
A further object of the invention is to fabricate the semiconductor structure by doping one side of a semiconductor wafer, machining or otherwise forming fluid passages into the wafer, and then joining two such wafers to provide a semiconductor structure which includes both a heating element and a cooling element.
A further object of the invention is to provide power to a region of a semiconductor layer doped such that application of the power to the region generates heat.
A further object of the invention is to pass cooling fluid through channels provided in a layer of a semiconductor device wherein the layer also provides heat.
A further object of the invention is for the heating and cooling sources produced by heating and cooling regions provided in a single semiconductor wafer to be co-mingled rather than stacked in series, so as to minimize system mass and thermal response time.
A still further object of the invention is to provide a vacuum feedthrough to enable a device to be vacuum held firmly on a structure.
A still further object of the invention is to provide a temperature control device having a precising structure to help guide and locate the device such that the device can be precisely and accurately located with respect to electrical test contactors.
A still further object of the invention is to integrate the temperature control device with the integrated circuit structure of a semiconductor device to eliminate the need for a mechanical contact interface between temperature control structure and semiconductor device structure, thus enabling direct temperature control of a semiconductor device with minimal energy requirements. This will enable a semiconductor device to operate at very low temperatures, and enable devices such as CMOS chips to run considerably faster and with lower leakage. For CMOS chips, speeds at liquid nitrogen temperature are 3 to 4 times that at room temperature, and device leakage is reduced by 3 orders of magnitude.
In accordance with the present invention, a temperature control structure includes a first electrically insulating layer having first and second opposing surfaces, a resistive layer having first and second opposing surfaces and having one or more channels provided therein with at least a portion of said resistive layer having a resistance characteristic such that a signal applied to the resistive layer causes heat to be generated, with the first surface of said resistive layer disposed over the first surface of said first electrically insulating layer. The temperature control structure further includes a second electrically insulating layer having first and second opposing surfaces with the first surface of said second electrically insulating layer disposed over the second surface of said heat generating layer.
With this particular arrangement, a temperature control structure for controlling the temperature of a circuit component is provided.
The resistive layer having the one or more channels can be provided from micromachined semiconductor wafers, such as silicon wafers. The wafers are doped such that application of power to the wafer results in heat generated by the semiconductor structure itself. A cooling fluid can be fed through the one or more channels provided directly in the resistive layer. In this manner the temperature control structure is provided having intermingled heating and cooling sources. This results in a system having a relatively low thermal mass and having a relatively rapid thermal response time. In one embodiment, the structure can be fabricated by diffusion bonding doped silicon wafers to provide the structure as an essentially monolithic structure. Because the temperature control structure is essentially monolithic, there are no differential thermal stresses to cause thermal fatigue, and there are no mechanical interfaces between elements which could create a variance in performance between systems. Furthermore, precising and vacuum clamping structures can be integrated into the temperature structure to locate and hold a component that is to be temperature controlled during testing.
It should be appreciated that the structures and techniques described herein have application to dynamic tri-temp testing as well as conventional handling applications in which a handler although capable of operating over a range of temperatures is operated only at a single temperature because of the time required to change the temperature from hot to cold or vice versa.
In accordance with a further aspect of the present invention, a method for controlling the temperature of a device under test comprises the steps of placing the device under test onto a semiconductor structure, monitoring a temperature of the device under test, providing a temperature signal having a characteristic which corresponds to the temperature of the device under test, comparing the temperature signal to a predetermined temperature signal threshold value, in response to the temperature signal being greater than the temperature signal threshold value, heating a layer of the semiconductor structure to a predetermined temperature level and in response to the temperature control signal being less than the temperature signal threshold value, cooling a layer of the semiconductor structure to a predetermined temperature level. To heat a layer of semiconductor structure, a signal can be applied to a resistive layer of the semiconductor structure. To cool a layer of semiconductor structure, a cooling fluid can be introduced into a channel of the semiconductor structure. With this particular arrangement, a technique for controlling the temperature of a device under test by applying signals and cooling fluid to a semiconductor structure is provided. This results in the ability to rapidly heat and cool the device under test. If the resistive layer of the semiconductor structure is co-mingled or interdigitated with the channel of the semiconductor structure into which the cooling channels are fed, a relatively rapid heating and cooling technique is provided.